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Connectivity line devices: reset and clock control (RCC)
RM0008
Bits 1:0 SW[1:0] : System clock Switch
Set and cleared by software to select SYSCLK source.
Set by hardware to force HSI selection when leaving Stop and Standby mode or in case of failure of
the HSE oscillator used directly or indirectly as system clock (if the Clock Security System is
enabled).
00: HSI selected as system clock
01: HSE selected as system clock
10: PLL selected as system clock
11: Not allowed
7.3.3
Clock interrupt register (RCC_CIR)
Address offset: 0x08
Reset value: 0x0000 0000
Access: no wait state, word, half-word and byte access
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
Reserved
CSSC
w
PLL3
RDYC
w
PLL2
RDYC
w
PLL
RDYC
w
HSE
RDYC
w
HSI
RDYC
w
LSE
RDYC
w
LSI
RDYC
w
15
Res.
14
PLL3
RDYIE
rw
13
PLL2
RDYIE
rw
12
PLL
RDYIE
rw
11
HSE
RDYIE
rw
10
HSI
RDYIE
rw
9
LSE
RDYIE
rw
8
LSI
RDYIE
rw
7
CSSF
r
6
PLL3
RDYF
r
5
PLL2
RDYF
r
4
PLL
RDYF
r
3
HSE
RDYF
r
2
HSI
RDYF
r
1
LSE
RDYF
r
0
LSI
RDYF
r
Bits 31:24 Reserved, always read as 0.
Bit 23 CSSC : Clock security system interrupt clear
This bit is set by software to clear the CSSF flag.
0: No effect
1: Clear CSSF flag
Bit 22 PLL3RDYC : PLL3 Ready Interrupt Clear
This bit is set by software to clear the PLL3RDYF flag.
0: No effect
1: Clear PLL3RDYF flag
Bit 21 PLL2RDYC : PLL2 Ready Interrupt Clear
This bit is set by software to clear the PLL2RDYF flag.
0: No effect
1: Clear PLL2RDYF flag
Bit 20 PLLRDYC : PLL ready interrupt clear
This bit is set by software to clear the PLLRDYF flag.
0: No effect
1: Clear PLLRDYF flag
Bit 19 HSERDYC : HSE ready interrupt clear
This bit is set by software to clear the HSERDYF flag.
0: No effect
1: Clear HSERDYF flag
118/995
Doc ID 13902 Rev 9
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